In the field of the high withstand voltage semiconductor device (power device) which controls the voltage exceeding several hundreds volts, since a large current is also applied, there is a need to provide element characteristics which suppress heat generation, that is, loss. Furthermore, it is desirable to implement a voltage drive element having a relatively small-sized drive circuit suffering little loss as a driving scheme of the gate controlling the voltage and current.
In recent years, for the reasons as described above, an insulated gate bipolar transistor, that is, an IGBT, has been mainly employed in this field as an element that allows voltage driving with little loss. This IGBT is configured so as to allow a decreased impurity concentration of the drain of a MOS (Metal Oxide Semiconductor) transistor for keeping the withstand voltage low and to set a diode to be on the drain side for decreasing the drain resistance.
Since the diode exhibits a bipolar behavior in the IGBT as described above, the source side and the drain side of the MOS transistor in the IGBT are referred to as an emitter side and a collector side, respectively, in the present application.
The IGBT serving as a voltage drive element is generally applied with a voltage of several hundreds volts between its collector and emitter, and the applied voltage is controlled by a gate voltage of ±several volts to several tens of volts. Furthermore, the IGBT is often used as an inverter, in which case the voltage between the collector and the emitter is low but a large current flows when the gate is turned on, and no current flows but the voltage between the collector and the emitter is high when the gate is turned off.
The IGBT is usually operated in the above-described mode. Thus, loss may include a steady loss which is the product of the current and the voltage in the ON state, and a switching loss during the period of transition between the ON state and the OFF state. The product of the leakage current and the voltage in the OFF state is considerably small, so that it can be negligible.
On the other hand, it is also important to prevent destruction of the element even under the abnormal conditions, for example, in the case where the load shorts out. In this case, the gate is turned on to cause a large current to flow while a power supply voltage of several hundreds volts is applied between the collector and the emitter.
In the IGBT configured to have a MOS transistor and a diode connected in series, the maximum current is limited by the saturation current of the MOS transistor. Accordingly, the current limitation occurs also in the case where a short circuit occurs as described above, which allows prevention of element destruction resulting from heat generation for a certain period of time.
The structure of the conventional IGBT is disclosed, for example, in Japanese Patent Laying-Open No. 2004-247593 (Patent Document 1). The IGBT in Patent Document 1 mainly includes a gate electrode, a source (emitter) electrode, a drain (collector) electrode, and an n-type substrate. A trench is formed on the upper surface of the n-type substrate, and the gate electrode is buried in this trench. A p-type base layer is formed on the upper portion in the n-type substrate, and an n+ type source layer and a p+ type drain layer are formed within the p-type base layer. The n+ type source layer and the p+ type drain layer are adjacent to each other on the surface of the n-type substrate. The gate electrode faces the n+ type source layer and the p-type base layer across the gate insulating film within the n-type substrate. The emitter electrode is in electrical contact with the n+ type source layer and the p+ type drain layer. The p+ type drain layer is formed on the underside of the n-type substrate, and the collector electrode is in contact with the p+ type drain layer on the underside of the n-type substrate. An n− type epitaxial layer and an n-type buffer layer are buried between the p+ type drain layer and the p-type base layer within the n-type substrate. The n− type epitaxial layer is in contact with the p-type base layer and the n-type buffer layer, and the n-type buffer layer is in contact with the p+ type drain layer.
Furthermore, the IGBT having the same configuration as that in Patent Document 1 is disclosed, for example, in Japanese Patent Laying-Open No. 2006-49933 (Patent Document 2), Japanese Patent Laying-Open No. 2002-359373 (Patent Document 3), Japanese Patent Laying-Open No. 09-260662 (Patent Document 4), U.S. Pat. No. 6,815,767 (Patent Document 5), U.S. Pat. No. 6,953,968 (Patent Document 6), and U.S. Pat. No. 6,781,199 (Patent Document 7).    Patent Document 1: Japanese Patent Laying-Open No. 2004-247593    Patent Document 2: Japanese Patent Laying-Open No. 2006-049933    Patent Document 3: Japanese Patent Laying-Open No. 2002-359373    Patent Document 4: Japanese Patent Laying-Open No. 09-260662    Patent Document 5: U.S. Pat. No. 6,815,767    Patent Document 6: U.S. Pat. No. 6,953,968    Patent Document 7: U.S. Pat. No. 6,781,199